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| Ordering number : EN*A1586 STK672-432A-E Overview Thick-Film Hybrid IC 2-phase Stepping Motor Driver The STK672-432A-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control. Applications * Office photocopiers, printers, etc. Features * Built-in overcurrent detection function (output current OFF). * Built-in overheat detection function (output current OFF). * If either over-current or overheat detection function is activated, the FAULT1 signal (active low) is output. The FAULT2 signal is used to output the result of activation of protection circuit detection at 2 levels. * Built-in power on reset function. * A micro-step sine wave-driven driver can be activated merely by inputting an external clock. * External pins can be used to select 2, 1-2 (including pseudo-micro), W1-2, 2 W1-2, or 4W1-2 excitation. * The switch timing of the 4-phase distributor can be switched by setting an external pin (MODE3) to detect either the rise and fall, or rise only, of CLOCK input. * Phase is maintained even when the excitation mode is switched. Rotational direction switching function. * Supports schmitt input for 2.5V high level input. * Incorporating a current detection resistor (0.152: resistor tolerance 2%), motor current can be set using two external resistors. * The ENABLE pin can be used to cut output current while maintaining the excitation mode. * With a wide current setting range, power consumption can be reduced during standby. * No motor sound is generated during hold mode due to external excitation current control. * A external excitation system is used for PWM operations. Fixed current control for shifting the phase of Ach/Bch is used for the PWM phase. * Miniature package (provides pin compatibility with STK672-430A-E) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. N1809HKIM No.A1586-1/21 STK672-432A-E Specifications Absolute Maximum Ratings at Tc = 25C Parameter Maximum supply voltage 1 Maximum supply voltage 2 Input voltage Output current 1 Output current 2 Allowable power dissipation 1 Allowable power dissipation 2 Operating substrate temperature Junction temperature Storage temperature Symbol VCC max VDD max VIN max IOP max IOH max PdMF max PdPK max Tc max Tj max Tstg No signal No signal Logic input pins 10s, 1 pulse (resistance load) VDD=5V, CLOCK200Hz With an arbitrarily large heat sink. Per MOSFET No heat sink Conditions Ratings 52 -0.3 to +6.0 -0.3 to +6.0 10 2.5 7.3 2.8 105 150 -40 to +125 unit V V V A A W W C C C Allowable Operating Ranges at Ta=25C Parameter Operating supply voltage 1 Operating supply voltage 2 Input high voltage Input low voltage Output current CLOCK frequency Phase driver withstand voltage Recommended operating substrate temperature Recommended Vref range Vref Tc=105C Symbol VCC VDD VIH VIL IOH fCL VDSS Tc With signals applied With signals applied Pins 10, 11, 12, 13, 14, 15, 17 Pins 10, 11, 12, 13, 14, 15, 17 Tc=105C, CLOCK200Hz Minimum pulse width: at least 10s ID=1mA (Tc=25C) No condensation Conditions Ratings 10 to 42 55% 2.5 to VDD 0 to 0.8 2.0 0 to 50 100min 0 to 105 0.14 to 1.48 unit V V V V A kHz V C V Electrical Characteristics at Tc=25C, VCC=24V, VDD=5.0V *1 Parameter VDD supply current Output average current *2 FET diode forward voltage Output saturation voltage Control input pin 5V level input current GND level input current Vref input bias current FAULT1 pin Output low voltage 5V level leakage current FAULT2 pin Overcurrent detection output voltage Overheat detection output voltage Overheat detection temperature PWM frequency TSD fc Design guarantee 41 144 48 55 C kHz VOF3 3.1 3.3 3.5 VOF2 Input voltage Symbol ICCO Ioave Vdf Vsat VIH VIL IILH IILL IIB VOLF IILF Conditions VDD=5.0V, ENABLE=Low R/L=1/0.62mH in each phase If=1A (RL=23) RL=23 Pins 10, 11, 12, 13, 14, 15, 17 Pins 10, 11, 12, 13, 14, 15, 17 Pins 10, 11, 12, 13, 14, 15, 17=5V Pins 10, 11, 12, 13, 14, 15, 17=GND Pin 19 =1.0V Pin 16 (IO=5mA) Pin 16 =5V Pin 8 (when all protection functions have been activated) 2.4 2.5 2.6 V 10 0.25 2.5 -0.3 50 0.19 min typ 5.7 0.23 1 0.35 max 7.0 0.27 1.6 0.50 VDD 0.8 75 10 15 0.5 10 unit mA A V V V V A A A V A Notes *1: A fixed-voltage power supply must be used. *2: The value for Ioave assumes that the lead frame of the product is soldered to the mounting circuit board. Continued on next page. No.A1586-2/21 STK672-432A-E Continued from preceding page. Parameter 4W1-2 4W1-2 4W1-2 4W1-2 A*B Chopper Current Ratio 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 4W1-2 2 2W1-2 2W1-2 W1-2 2W1-2 2W1-2 W1-2 1-2 Vref *3 2W1-2 2W1-2 W1-2 2W1-2 2W1-2 W1-2 1-2 Symbol =15/16, 16/16 =14/16 =13/16 =12/16 =11/16 =10/16 =9/16 =8/16 =7/16 =6/16 =5/16 =4/16 =3/16 =2/16 =1/16 Conditions min typ 100 97 95 93 87 83 77 71 64 55 47 40 30 20 11 100 % max unit Notes *3: The values given for Vref are design targets, no measurement is performed. Package Dimensions unit:mm (typ) 24.2 (18.4) (R1.47) 4.5 (11.0) 14.4 1 19 (3.5) 11.0 1.0 18 1.0=18.0 0.5 0.4 2.0 4.0 4.45 14.4 No.A1586-3/21 STK672-432A-E Derating Curve of Motor Current, IOH, vs. Operating Substrate Temperature, Tc 3.0 IOH - Tc 200Hz 2 phase excitation 2.5 Motor current, IOH - A Hold mode 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 90 100 110 ITF02592 Operating Substrate Temperature, Tc- C Notes * The current range given above represents conditions when output voltage is not in the avalanche state. * If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-4** series hybrid ICs given in a separate document. * The operating substrate temperature, Tc, given above is measured while the motor is operating. Because Tc varies depending on the ambient temperature, Ta, the value of IOH, and the continuous or intermittent operation of IOH, always verify this value using an actual set. * The Tc temperature should be checked in the center of the metal surface of the product package. No.A1586-4/21 STK672-432A-E Block Diagram VDD 9 MOI FAULT2 Vref 7 19 8 A 4 AB 5 B 3 BB 1 MODE1 10 MODE2 11 CWB 13 CLOCK 12 Excitation mode selection Rising edge / falling edge detection Phase advance counter 1/4.9 Current divider ratio switching Pseudo sine wave generator VSS + 100k MODE3 17 RESETB 14 Power-on reset Phase excitation signal generator Overcurrent detection ENABLE 15 Latch Overheating detection Oscillator FAULT1 16 S.G 18 Reference clock generator PWM control + + 2 P.G1 6 P.G2 SUB Sample Application Circuit STK672-432A-E VDD=5V 10 11 17 CLOCK ENABLE CWB MOI RESETB 14 R01 C02 10F + R02 8 S.G FAULT1 FAULT2 16 18 Vref 19 2 6 P.G1 12 4 15 13 7 5 3 1 A AB B BB + C01 100F VCC=24V 2-phase stepping motor 9 P.G2 P.GND No.A1586-5/21 STK672-432A-E Precautions [GND wiring] * To reduce noise on the 5V/24V system, be sure to place the GND of C01 in the circuit given above as close as possible to Pin 2 and Pin 6 of the hybrid IC. In addition, in order to set the current accurately, the GND side of RO2 of Vref must be connected to the shared ground terminal used by the Pin 18 (S.G) GND, P.G1 and P.G2. [Input pins] * When VDD is being input, for each input pin, measures must be taken so that a negative voltage less than -0.3V is not applied to Pin 18. Measures must also be taken so that a voltage equal to or greater than VDD is not input. * High voltage input other than VDD, MOI, FAULT1, and FAULT2 is 2.5V. * Pull-up resistors are not connected to input pins. Pull-down resistors are attached. When controlling the input to the hybrid IC with the open collector type, be sure to connect a pull-up resistor (1 to 20k). Be sure to use a device (0.8V or less, low level, when IOL=5mA) for the open collector driver at this time that has an output voltage specification such that voltage is pulled to less than 0.8V at low level. * When using the power on reset function built into the hybrid IC, be sure to directly connect Pin 14 to VDD. * We recommend attaching a 1,000pF capacitor to each input to prevent malfunction during high-impedance input. Be sure to connect the capacitor near the hybrid IC, between Pin 18 (S, G). When input is fixed low, directly connect to Pin 18. When input is fixed high, directly connect to VDD. [Current setting Vref] * We recommend a resistance of 1k or less for RO2 to reduce the effect of input bias current to the Vref pin. * If the motor current is temporarily reduced, the circuit given below is recommended. The variable voltage range of Vref input is 0.14 to 1.48V. 5V RO1 Vref R3 RO2 5V RO1 Vref R3 RO2 [Setting the motor current] The motor current, IOH, is set using the Pin 19 voltage, Vref, of the hybrid IC. Equations related to IOH and Vref are given below. Vref (RO2 / (RO2+RO1))xVDD(5V) ********************************************************* (1) IOH (Vref / 4.9) / Rs ********************************************************************************** (2) The value of 4.9 in Equation (2) above represents the Vref voltage as divided by a circuit inside the control IC. Rs: 0.152 (Current detection resistor inside the hybrid IC) No.A1586-6/21 STK672-432A-E * Motor current peak value IOH setting IOH 0 [Smoke Emission Precuations] If Pin 18 (S.G terminal) is attached to the PCB without using solder, overcurrent may flow into the MOSFET at VCCON (24V ON), to emit smoke because 5V circuits cannot be controlled. In addition, as long as one of the output Pins, 1, 3, 4, or 5, is open, inductance energy stored in the motor results in electrical stress on the driver, possibly resulting in the emission of smoke. Function Table M2 M1 M3 1 0 0 2-phase excitation selection 1-2 phase excitation (IOH=100%, 71%) 0 1 1-2-phase excitation (IOH=100%) W1-2 phase excitation 1 0 W1-2 phase excitation 2W1-2 phase excitation 1 1 2W1-2 phase excitation 4W1-2 phase excitation CLOCK Edge Timing for Phase Switching CLOCK rising edge 0 CLOCK both edges IOH=100% results in the Vref voltage setting, IOH. During 1-2 phase excitation, the hybrid IC operates at a current setting of IOH=100% when the CLOCK signal rises. Conversely, pseudo micro current control is performed to control current at IOH=100% or 71% at both edges of the CLOCK signal. CWB pin Forward/CW Reverse/CCW 0 1 ENABLE * RESETB pin ENABLE RESETB Motor current cut: Low Active Low No.A1586-7/21 STK672-432A-E Timing Charts 2-phase excitation timing charts (M3=1) M1 M2 M3 RESET CWB MOSFET Gate Signal CLK A A B B MOI 100% 0 0 1 0 1-2-phase excitation timing charts (M3=1) M1 M2 M3 RESET CWB MOSFET Gate Signal Comparator Reference Voltage ITF02580 1 0 0 1 0 CLK A A B B MOI 100% 71% Comparator Reference Voltage 71% A phase Vref 100% 71% A phase Vref 100% 71% B phase Vref B phase Vref ITF02581 W1-2-phase excitation timing charts (M3=1) M1 M2 M3 RESET CWB MOSFET Gate Signal CLK A A B B MOI 100% 92% 71% 40% 2W1-2-phase excitation timing charts (M3=1) M1 M2 M3 RESET CWB MOSFET Gate Signal Comparator Reference Voltage ITF02582 1 0 1 0 1 0 0 1 0 1 0 CLK A A B B MOI 100% 97% 92% 83% 71% 55% 40% 20% Comparator Reference Voltage A phase Vref 100% 92% 71% 40% A phase Vref 100% 97% 92% 83% 71% 55% 40% 20% B phase Vref B phase Vref ITF02583 No.A1586-8/21 STK672-432A-E 1-2-phase excitation timing charts (M3=0) M1 M2 M3 RESET CWB MOSFET Gate Signal 0 0 0 W1-2-phase excitation timing charts (M3=0) M1 M2 M3 RESET CWB MOSFET Gate Signal Comparator Reference Voltage ITF02584 1 0 0 0 CLK A A B B MOI 100% CLK A A B B MOI 100% 92% 71% 40% Vref 100% 92% 71% 40% Vref ITF02585 Comparator Reference Voltage 71% A phase Vref 100% 71% A phase B phase Vref B phase 2W1-2-phase excitation timing charts (M3=0) M1 M2 M3 RESET CWB MOSFET Gate Signal 4W1-2-phase excitation timing charts (M3=0) M1 M2 M3 RESET CWB MOSFET Gate Signal 1 0 1 0 0 0 1 0 0 CLK A A B B MOI 100% 97% 92% 83% 71% 55% 40% 20% Vref 100% 97% 92% 83% 71% 55% 40% 20% Vref ITF02586 CLK A A B B MOI 97% 92% 83% 71% 100% 95% 88% 77% 64% 55% 47% 40% 30% 20% 11% Vref 100% 95% 88% 77% 64% 55% 47% 40% 30% 20% 11% Vref ITF02587 Comparator Reference Voltage A phase Comparator Reference Voltage A phase 97% 92% 83% 71% B phase B phase No.A1586-9/21 STK672-432A-E Usage Notes 1. I/O Pins and Functions of the Control Block [Pin description] HIC pin 7 19 10 11 17 12 13 14 15 16 8 Pin Name MOI Vref MODE1 MODE2 MODE3 CLOCK CWB RESETB ENABLE FAULT1 FAULT2 Overcurrent/over-heat detection output External CLOCK (motor rotation instruction) Sets the direction of rotation of the motor axis System reset Motor current OFF Excitation mode selection Function Output pin for the excitation monitor Current value setting Description of each pin [CLOCK (Phase switching clock)] Input frequency: DC-20kHz (when using both edges) or DC-50kHz (when using one edge) Minimum pulse width: 20s (when using both edges) or 10s (when using one edge) Pulse width duty: 40% to 50% Both edge, single edge operation M3:1 The excitation phase moves one step at a time at the rising edge of the CLOCK pulse. M3:0 The excitation phase moves alternately one step at a time at the rising and falling edges of the CLOCK pulse. [CWB (Motor direction setting)] When CWB=0: The motor rotates in the clockwise direction. When CWB=1: The motor rotates in the counterclockwise direction. Do not allow CWB input to vary during the 7s interval before and after the rising and falling edges of CLOCK input. [ENABLE (Forcible OFF control of excitation drive output A, AB, B, and BB, and selecting operation/hold status inside the HIC)] ENABLE=1: Normal operation When ENABLE=0: Motor current goes OFF, and excitation drive output is forcibly turned OFF. The system clock inside the HIC stops at this time, with no effect on the HIC even if input pins other than RESET input vary. In addition, since current does not flow to the motor, the motor shaft becomes free. If the CLOCK signal used for motor rotation suddenly stops, the motor shaft may advance beyond the control position due to inertia. A SLOW DOWN setting where the CLOCK cycle gradually decreases is required in order to stop at the control position. [MODE1, MODE2, and MODE3 (Selecting the excitation mode, and selecting one edge or both edges of the CLOCK)] Excitation select mode terminal (See the sample application circuit for excitation mode selection), selecting the CLOCK input edge(s). Mode setting active timing Do not change the mode within 7s of the input rising or falling edge of the CLOCK signal. [RESETB (System-wide reset)] The reset signal is formed by the power-on reset function built into the HIC and the RESETB terminal. When activating the internal circuits of the HIC using the power-on reset signal within the HIC, be sure to connect Pin 14 of the HIC to VDD. No.A1586-10/21 STK672-432A-E [Vref (Voltage setting to be used for the current setting reference)] * Pin type: Analog input configuration, input pull-down resistor 100k Input voltage is in the voltage range of 0.14V to 1.48V. [Input timing] The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate voltage is 5V5%, conduction of current to output at the time of power on reset adds electromotive stress to the MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while VDD, which is outside the operating supply voltage, is less than 4.75V. In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10s until CLOCK input. 4Vtyp Control IC power (VDD) rising edge Control IC power on reset 3.8Vtyp RESETB signal input No time specification ENABLE signal input CLOCK signal input At least 10s At least 10s ENABLE, CLOCK, and RESETB Signals Input Timing [Configuration of control block I/O pins] 5V Output pin Pin 8 5V 50k 50k Overcurrent 10k Input pin 100k VSS 50k Thermal shutdown The input pins of this driver all use Schmitt input. Typical specifications at Tc=25C are given below. Hysteresis voltage is 0.3V (VIHa-VILa). When rising When falling 1.8Vtyp Input voltage VIHa VILa 1.5Vtyp No.A1586-11/21 STK672-432A-E Input voltage specifications are as follows. VIH=2.5Vmin VIL=0.8Vmax 5V Vref/4.9 + Amplifier 100k VSS VSS Input pin Pin 19 Thermal shutdown VSS (The buffer has an open drain configuration.) Output pin Pin 16 Overcurrent No.A1586-12/21 STK672-432A-E 2. Overcurrent Detection and Overheat Detection Functions Each detection function operates using a latch system and turns output off. Because a RESET signal is required to restore output operations, once the power supply, VDD, is turned off, you must either again apply power on reset with VDDON or apply a RESETB=HighLowHigh signal. [Overcurrent detection] This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there is a short between the motor terminals. Overcurrent detection occurs at 3.4A typ with the STK672-432A-E. Current when motor terminals are shorted PWM period Set motor current, IOH Overcurrent detection IOHmax MOSFET all OFF No detection interval (1.25s typ) Normal operation 1.25s typ Operation when motor pins are shorted Overcurrent detection begins after an interval of no detection (a dead time of 1.25s typ) during the initial ringing part during PWM operations. The no detection interval is a period of time where overcurrent is not detected even if the current exceeds IOH. [Overheat detection] Rather than directly detecting the temperature of the semiconductor device, overheat detection detects the temperature of the aluminum substrate (144C typ). Within the allowed operating range recommended in the specification manual, if a heat sink attached for the purpose of reducing the operating substrate temperature, Tc, comes loose, the semiconductor can operate without breaking. However, we cannot guarantee operations without breaking in the case of operations other than those recommended, such as operations at a current exceeding IOH max that occurs before overcurrent detection is activated. No.A1586-13/21 STK672-432A-E 3. Allowable Avalanche Energy Value (1) Allowable Range in Avalanche Mode When driving a 2-phase stepping motor with constant current chopping using an STK672-4** Series hybrid IC, the waveforms shown in Figure 1 below result for the output current, ID, and voltage, VDS. VDSS: Voltage during avalanche operations VDS IOH: Motor current peak value IAVL: Current during avalanche operations ID tAVL: Time of avalanche operations ITF02557 Figure 1 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-4** Series when Driving a 2Phase Stepping Motor with Constant Current Chopping When operations of the MOSFET built into STK672-4** Series ICs is turned off for constant current chopping, the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly rises due to electromagnetic induction generated by the motor coil. In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at this time, EAVL1, is represented by Equation (3-1). EAVL1=VDSSxIAVLx0.5xtAVL ------------------------------------------- (3-1) VDSS: V units, IAVL: A units, tAVL: sec units The coefficient 0.5 in Equation (3-1) is a constant required to convert the IAVL triangle wave to a square wave. During STK672-4** Series operations, the waveforms in the figure above repeat due to the constant current chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (3-2) used to find the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (3-1). PAVL=VDSSxIAVLx0.5xtAVLxfc ------------------------------------------- (3-2) fc: Hz units (fc is set to the PWM frequency of 50kHz.) For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-4** Series and substitute values when operations are observed using an oscilloscope. Ex. If VDSS=110V, IAVL=1A, tAVL=0.2s when using a STK672-432A-E driver, the result is: PAVL=110x1x0.5x0.2x10-6x50x103=0.55W VDSS=110V is a value actually measured using an oscilloscope. The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3. When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL waveforms during operation, and then check that the result of calculating Equation (3-2) falls within the allowable range for avalanche operations. No.A1586-14/21 STK672-432A-E (2) ID and VDSS Operating Waveforms in Non-avalanche Mode Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during actual operations. Factors causing avalanche are listed below. * Poor coupling of the motor's phase coils (electromagnetic coupling of A phase and AB phase, B phase and BB phase). * Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor. * Increases in VDSS, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V. If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as shown in Figure 2. Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss range of PAVL shown in Figure 3. VDS IOH: Motor current peak value ID ITF02558 Figure 2 Output Current, ID, and Voltage, VDS, Waveforms 2 of the STK672-4** Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping Figure 3 Allowable Loss Range, PAVL-IOH During Avalanche Operations Average power loss in the avalanche state, PAVL- W 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 ITF02593 PAVL - IOH Tc= 80 C 105 C Motor current,IOH - A Note: The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. Because it is possible to apply 2.6W or more at IOH=0A, be sure to avoid using the MOSFET body diode that is used to drive the motor as a zener diode. No.A1586-15/21 STK672-432A-E 4. Calculating HIC Internal Power Loss The average internal power loss in each excitation mode of the STK672-432A-E can be calculated from the following formulas. *1 [Each excitation mode] 2-phase excitation mode 2PdAVex= (Vsat+Vdf) x0.5xCLOCKxIOHxt2+0.5xCLOCKxIOHx (Vsatxt1+Vdfxt3) --------------------------- (4-1) 1-2 Phase excitation mode 1-2PdAVex= (Vsat+Vdf) x0.25xCLOCKxIOHxt2+0.25xCLOCKxIOHx (Vsatxt1+Vdfxt3) ---------------------- (4-2) W1-2 Phase excitation mode W1-2PdAVex=0.64[(Vsat+Vdf) x0.125xCLOCKxIOHxt2+0.125xCLOCKxIOHx (Vsatxt1+Vdfxt3)] ---------- (4-3) 2W1-2 Phase excitation mode 2W1-2PdAVex=0.64[(Vsat+Vdf) x0.0625xCLOCKxIOHxt2+0.0625xCLOCKxIOHx (Vsatxt1+Vdfxt3)] ------ (4-4) 4W1-2 Phase excitation mode 4W1-2PdAVex=0.64[(Vsat+Vdf) x0.0625xCLOCKxIOHxt2+0.0625xCLOCKxIOHx (Vsatxt1+Vdfxt3)] ------ (4-5) Motor hold mode HoldPdAVex= (Vsat+Vdf) xIOH---------------------------------------------------------------------------------------------- (4-6) Note: 2-phase 100% conductance is assumed in Equation (4-6). Vsat: Combined voltage of Ron voltage drop + current detection resistance Vdf: Combined voltage of the FET body diode + current detection resistance *1 CLOCK: Input CLOCK (HIC: input frequency at Pin 12) *1 Although a synchronous rectification system is used, substitute using the value of Vdf, while taking design margins into account. t1, t2, and t3 represent the waveforms shown in the figure below. t1: Time required for the winding current to reach the set current (IOH) t2: Time in the constant current control (PWM) region t3: Time from end of phase input signal until inverse current regeneration is complete IOH 0A t1 t2 t3 Motor COM Current Waveform Model t1= (-L/(R+0.35)) In (1-(((R+0.35)/VCC) xIOH)) --------------------------------------------------------------- (4-7) t3= (-L/R) In ((VCC+1)/(IOHxR+VCC+1)) --------------------------------------------------------------------- (4-8) VCC: Motor supply voltage (V) L: Motor inductance (H) R: Motor winding resistance () IOH: Motor set output current crest value (A) No.A1586-16/21 STK672-432A-E Fixed current control time, t2, for each excitation mode (1) 2-phase excitation (2) 1-2 phase excitation (3) W1-2 phase excitation (4) 2W1-2 phase excitation (and 4W1-2 phase excitation) t2 = (2/CLOCK) - (t1 + t3)*******************************(4-9) t2 = (3/CLOCK) - t1*****************************************(4-10) t2 = (7/CLOCK) - t1*****************************************(4-11) t2 = (15/CLOCK) - t1***************************************(4-12) For the values of Vsat and Vdf, be sure to substitute from Vsat vs IOH and Vdf vs IOH at the setting current value IOH. (See pages to follow) Then, determine if a heat sink is necessary by comparing with the Tc vs Pd graph (see next page) based on the calculated average output loss, HIC. For heat sink design, be sure to see STK672-432A-E. The HIC average power, PdAVex described above, represents loss when not in avalanche mode. To add the loss in avalanche mode, be sure to add PAVL (4-13, 14) using the formula (3-2) for average power loss , PAVL, for STK6724** avalanche mode, described below to PdAVex described above. When using this IC without a fin, always check for temperature increases in the set, because the HIC substrate temperature, Tc, varies due to effects of convection around the HIC. [Calculating the average power loss, PAVL, during avalanche mode] The allowable avalanche energy, EAVL, during fixed current chopping operation is represented by Equation (3-2) used to find the average power loss, PAVL, during avalanche mode that is calculated by multiplying Equation (3-1) by the chopping frequency. PAVL=VDSSxIAVLx0.5xtAVLxfc ******************************************************************************************************(3-2) fc: Hz units (input MAX PWM frequency when using the STK672-4** series.) Be sure to actually operate an STK672-4** series and substitute values found when observing operations on an oscilloscope for VDSS, IAVL, and tAVL. The sum of PAVL values for each excitation mode is multiplied by the constants given below and added to the average internal HIC loss equation, except in the case of 2-phase excitation. 1-2 excitation mode and higher: PAVL(1)=0.7xPAVL********************************************************************* (4-13) During 2-phase excitation and motor hold: PAVL(1)=1xPAVL ******************************************************* (4-14) No.A1586-17/21 STK672-432A-E Output saturation voltage, Vsat - Output current, IOH 1.0 Vsat - IOH Output saturation voltage, Vsat - V 0.8 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 ITF02594 Output current, IOH - A Forward voltage, Vdf -Output current, IOH 1.4 1.2 Forward voltage, Vdf - V 1.0 25 Tc =1 05 C C Vdf- IOH 25C Tc= 105 C 0.8 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 ITF02595 Output current, IOH - A Substrate temperature rise, Tc (no heat sink) - Internal average power dissipation, PdAV 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 ITF02717 Tc - PdAV Substrate temperature rise, Tc - C Hybrid IC internal average power dissipation, PdAV - W No.A1586-18/21 STK672-432A-E 5. Thermal design [Operating range in which a heat sink is not used] Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the quality of the HIC. The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC. The value of PdAV increases as the output current increases. To calculate PdAV, refer to "Calculating Internal HIC Loss for the STK672-432A-E". Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, IO1 Motor phase current (sink side) IO2 0A -IO1 T1 T3 T2 T0 Figure 1 Motor Current Timing T1: Motor rotation operation time T2: Motor hold operation time T3: Motor current off time T2 may be reduced, depending on the application. T0: Single repeated motor operating cycle IO1 and IO2: Motor current peak values Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. The hybrid IC internal average power dissipation PdAV can be calculated from the following formula. PdAV= (T1xP1+T2xP2+T3x0) /TO ---------------------------- (I) (Here, P1 is the PdAV for IO1 and P2 is the PdAV for IO2) If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60C or less, there is no need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used. [Operating range in which a heat sink is used] Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of c-a in Equation (II) below and the graph depicted in Figure 3. c-a= (Tc max-Ta) /PdAV ---------------------------- (II) Tc max: Maximum operating substrate temperature =105C Ta: HIC ambient temperature Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and confirm that the substrate temperature, Tc, is 105C or less. The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation. To add the loss during avalanche operations, be sure to add Equation (3-2), "Allowable STK672-4** Avalanche Energy Value", to PdAV. No.A1586-19/21 STK672-432A-E Figure 2 Substrate temperature rise, Tc - Internal average power dissipation, PdAV 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 ITF02717 Tc - PdAV Substrate temperature rise, Tc - C Hybrid IC internal average power dissipation, PdAV - W Figure 3 Heat sink area (Board thickness: 2mm) - c-a 100 c-a - S Heat sink thermal resistance, c-a - C/W 7 5 3 2 10 7 5 3 2 Wit h no Wit h a fl at b l nish ack surf ace fini sh surf ace fi 1.0 10 2 3 5 7 100 2 3 5 7 1000 ITF02554 Heat sink area, S - cm2 No.A1586-20/21 STK672-432A-E 6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink. The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta. Power loss of up to 2.8W is allowable at Ta=25C, and of up to 1.5W at Ta=60C. Allowable power dissipation, PdPK (no heat sink) - Ambient temperature, Ta 3.0 PdPK - Ta Allowable power dissipation, PdPK - W 2.5 2.0 1.0 1.5 0.5 0 0 20 40 60 80 100 120 ITF02718 Ambient Temperature, Ta - C SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2009. Specifications and information herein are subject to change without notice. PS No.A1586-21/21 |
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